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| CMA3000-D01 Data Sheet CMA3000-D01 3-AXIS ULTRA LOW POWER ACCELEROMETER WITH DIGITAL SPI AND I2C INTERFACE Features * * * * * * * * * 1.7 V - 3.6 V supply voltage SPI and I2C digital interface User selectable * 2 g and 8 g measurement ranges * sample rate & frequency response Ultra low current consumption * 70 uA with 100/400 Hz sample rate * 11 uA with 40/10Hz sample rate Interrupt signal triggered by data ready, motion and free fall Size 2x2x0.95 mm3 Proven capacitive 3D-MEMS technology High shock durability RoHS compliant / lead free soldering Applications CMA3000-D01 is targeted to battery operated devices. Typical applications are but not limited * Gaming input devices * Computer peripherals * Free fall detection * Activity monitoring C/V Analog calibration & ADC DEMUX 1:3 Low-pass Filter Low-pass Filter Low-pass Filter SCK/SCL SPI & I2C i/f MISO MOSI/SDA CSB Oscillator & clock Reference NonVolatile Memory Motion detector Free fall detector Control & INT INT Figure 1 CMA3000-D01 Block Diagram VTI Technologies Oy www.vti.fi PRELIMINARY - Subject to changes Doc. Nr. 8277800.14 1/4 Rev. 13 CMA3000-D01 Performance Characteristics 1) Parameter Vdd Digital I/O Vdd Operating temperature ** Current consumption * Condition Typical supply range 1.7 - 2.7 V Min Typ 2) Max 1.7 1.7 -40 -8 -2 -100 2.5 1.8 / 2.5 70 50 11 7 4 25 1 2.5 56 14 0.02 1.5 1 400 100 40 10 ODR/5 13 25 0.01 2.5/ODR 2.7 2.7 85 90 9 8 2 +100 Extended supply range 2.7 - 3.6 V Min Typ 2) Max -40 3.3 3.3 70 50 14 9 3 8 2 100 1 2.5 56 14 10 0.02 1.5 1 400 100 40 10 ODR/5 13 25 0.01 2.5/ODR 85 - Units V V C A Vdd Digital I/O Vdd ODR=400 Hz ODR=100 Hz ODR=40 Hz ODR=10 Hz Power down G_RANGE bit 0 G_RANGE bit 1 G_RANGE bit 1 -40 ... +85 C X and Z axis Y axis Full scale = 2 g Full scale = 8 g -40 ... +85 C G_RANGE bit 1 MODE bits x10 MODE bits x01 MODE bits 011 MODE bits 100 Full scale=2 g, ODR=100 Hz Full scale=8 g, ODR=400 Hz ODR=400 Hz ODR100 Hz Acceleration range * Offset calibration error * 3) Offset temperature error ** 4) Sensitivity * 5) Sensitivity calibration error * Sensitivity temperature error ** 6) Non-Linearity ** 7) Cross-Axis sensitivity ** 8) Output Data Rate, ODR ** G mg mg/C Count/g % %/C % FS % Hz -10 - +10 3 - Bandwidth** 9) Noise ** 10) - - 400 500 Hz mg RMS s kHz kHz Turn on time ** 11) I2C clock rate ** SPI clock rate ** * ** 1) 2) 3) 4) 5) 6) 7) 8) 400 500 9) 10) 100% tested in production Qualified during product validation The product is factory calibrated at 2.5 V in room temperature. Typical values are not guaranteed. Z-axis +1g position. Soldering process can cause offset shift which is typically less than 150 mg. Please see TN68_CMA3000_Assembly_Instructions for further details. Offset temperature error = {Count(0g)-Offset} / Sensitivity [ g ]. Sensitivity = Calibrated sensitivity. Offset= Calibrated offset. Sensitivity = {Count(+1g) - Count(-1g)}/2 [Count/g]. Sensitivity temperature error = {[Count(+1g)-Count(-1g)]/2 - Sensitivity} / Sensitivity x 100% [%]. Sensitivity = Calibrated sensitivity. Best fit straight line. The cross-axis sensitivity determines how much acceleration, perpendicular to the measuring axis, couples to the output. The total cross-axis sensitivity is the geometric sum of the sensitivities of the two axes which are perpendicular to the measuring axis. The angular alignment error between X, Y and Z axis is included into the cross axis sensitivity. Frequency responses with 1st order roll off according to Figure 3. Average noise/axis over the measurement bandwidth defined as 1 (n 2 + n 2 + n 2 ) , where nx, ny and nz are y x z 3 11) the measured signal's standard deviation due to noise in x, y and z directions. Settling error less than 1% of FS. VTI Technologies Oy www.vti.fi PRELIMINARY - Subject to changes Doc. Nr. 8277800.14 2/4 Rev. 14 CMA3000-D01 Figure 2 Package dimensions in mm with 50 m tolerance. ODR/500 ODR/50 ODR/5 ODR/500 ODR/50 ODR/5 Figure 3 Typical Frequency responses of CMA3000-D01. VTI Technologies Oy www.vti.fi PRELIMINARY - Subject to changes Doc. Nr. 8277800.14 3/4 Rev. 14 CMA3000-D01 SPI VDD 1 2 DVIO MISO 100n 100n 3 4 VDD VSS DVIO MISO INT CSB MOSI_SDA SCK_SCL 8 7 6 5 INT CSB MOSI DVIO SCK I2C VDD 1 2 3 4 VDD VSS DVIO MISO INT CSB MOSI_SDA SCK_SCL 8 7 6 5 SDA SCL INT 100n 100n Figure 4 Application schematics for SPI and I2C bus Note the symmetrical ground plane under the component. Figure 5 Recommended layout pattern (not actual size, for reference only) Table 1 Pin descriptions Pin # 1 2 3 4 5 6 7 8 Name VDD VSS DVIO MISO SCK_SCL MOSI_SDA CSB INT Function Supply voltage Ground I/O Supply SPI Serial Data Output (MISO) SPI Serial Clock (SCK) / I2C Serial Clock (SCL) SPI Serial Data Input (MOSI) / I2C Serial Data (SDA) Chip select / I2C enable Interrupt Document Change Control Rev. 0.1 ... 0.7 0.8 0.9 0.10 0.11 0.12 0.13 0.14 Date 02-May-07 ... 14-Feb-08 21-Apr-08 01-Jul-08 28-Aug-08 01-Sep-08 10-Dec-08 29-Dec-08 12-Jun-09 Change Description 1st version ... Performance characteristics update Target values for offset and sensitivity, non-linearity and cross axis added. Figure 1 & Table 1 pin names corrected, Figure 2,3 & 5 updated Current consumption, sensitivity and sensitivity temperature error, non-linearity, cross axis sensitivity and noise updated. 8g range noise level corrected. Performance characteristics and notes updated. Figure 2 updated. Version for launch Performance characteristics update PRELIMINARY - Subject to changes Doc. Nr. 8277800.14 4/4 Rev. 14 VTI Technologies Oy www.vti.fi |
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